A memory controller, also called memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of knowledge going to and from a pc’s fundamental memory. When a Memory Wave Workshop controller is built-in into another chip, akin to an integral a part of a microprocessor, it’s usually known as an integrated memory controller (IMC). Memory controllers contain the logic necessary to read and write to dynamic random-entry memory (DRAM), and to offer the critical Memory Wave refresh and other capabilities. Studying and writing to DRAM is performed by choosing the row and column information addresses of the DRAM as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM makes use of the transformed inputs to pick out the proper memory location and return the data, which is then handed again via a multiplexer to consolidate the data so as to reduce the required bus width for the operation. Memory controllers’ bus widths range from 8-bit in earlier methods, to 512-bit in additional difficult techniques, where they are usually carried out as four 64-bit simultaneous memory controllers operating in parallel, though some function with two 64-bit Memory Wave controllers being used to entry a 128-bit memory machine.

Some memory controllers, such as the one built-in into PowerQUICC II processors, include error detection and correction hardware. Many fashionable processors are also integrated memory management unit (MMU), which in many operating methods implements virtual addressing. On early x86-32 processors, the MMU is integrated in the CPU, however the memory controller is normally part of northbridge. Older Intel and PowerPC-based mostly computer systems have memory controller chips which might be separate from the main processor. Usually these are built-in into the northbridge of the computer, additionally typically known as a memory controller hub. Most trendy desktop or workstation microprocessors use an built-in memory controller (IMC), together with microprocessors from Intel, AMD, and those built across the ARM structure. Prior to K8 (circa 2003), AMD microprocessors had a memory controller applied on their motherboard’s northbridge. In K8 and later, AMD employed an integrated memory controller. Likewise, until Nehalem (circa 2008), Intel microprocessors used memory controllers implemented on the motherboard’s northbridge.

Nehalem and later switched to an integrated memory controller. Different examples of microprocessor architectures that use built-in memory controllers include NVIDIA’s Fermi, IBM’s POWER5, and Solar Microsystems’s UltraSPARC T1. Whereas an built-in memory controller has the potential to increase the system’s efficiency, similar to by lowering memory latency, it locks the microprocessor to a selected type (or types) of memory, forcing a redesign in order to support newer memory applied sciences. When DDR2 SDRAM was introduced, AMD launched new Athlon sixty four CPUs. These new fashions, with a DDR2 controller, use a distinct bodily socket (generally known as Socket AM2), in order that they are going to solely fit in motherboards designed for the brand new type of RAM. When the memory controller just isn’t on-die, the identical CPU could also be installed on a brand new motherboard, with an updated northbridge to make use of newer memory. Some microprocessors in the 1990s, such as the DEC Alpha 21066 and HP PA-7300LC, had built-in memory controllers